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TISP4xxxH3/M3BJ Series for LCAS Protection
Electrical Characteristics, TISP4xxxH3, TA = 25 ° C (Unless Otherwise Noted)
Parameter
Test Conditions
Min
Typ
Max
Unit
I DRM
V (BO)
Repetitive peak off-
state current
Breakover voltage
V D = V DRM
dv/dt = ± 250 V/ms, R SOURCE = 300 ?
T A = 25 ° C
T A = 85 ° C
‘4125
‘4219
± 5
± 10
± 125
±219
μ A
V
dv/dt ≤ ± 1000 V/ μ s, Linear voltage ramp,
V (BO)
Impulse breakover
voltage
Maximum ramp value = ± 500 V
di/dt = ± 20 A/ μ s, Linear current ramp,
‘4125
‘4219
± 134
± 229
V
Maximum ramp value = ± 10 A
I (BO)
V T
I H
dv/dt
I D
Breakover current
On-state voltage
Holding current
Critical rate of rise of
off-state voltage
Off-state current
dv/dt = ± 250 V/ms, R SOURCE = 300 ?
I T = ± 5 A, t W = 100 μ s
I T = ± 5 A, di/dt = +/-30 mA/ms
Linear voltage ramp, Maximum ramp value < 0.85V DRM
V D = ± 50 V
f = 1 MHz, V d = 1 V
rms, V D = 0,
f = 1 MHz, V d = 1 V
rms, V D = -1 V
T A = 85 ° C
± 0.15
± 0.15
± 5
80
71
± 0.6
± 3
± 0.6
± 10
90
79
A
V
A
kV/ μ s
μ A
C off
Off-state capacitance
f = 1 MHz, V d = 1 V
f = 1 MHz, V d = 1 V
rms, V D = -2 V
rms, V D = -50 V
65
30
74
35
pF
f = 1 MHz, V d = 1 V
rms, V D = -100 V
23
28
(see Note 5)
NOTE 5: To avoid possible voltage clipping, the ‘4125 is tested with V D = -98 V.
Thermal Characteristics
Parameter
R θ JA Junction to free air thermal resistance
Test Conditions
EIA/JESD51-3 PCB, I T = I TSM(1000) ,
T A = 25 ° C, (see Note 6)
265 mm x 210 mm populated line card,
4-layer PCB, I T = I TSM(1000) , T A = 25 ° C
Min
Typ
50
Max
113
Unit
° C/W
NOTE
6: EIA/JESD51-2 environment and the PCB has standard footprint dimensions connected with 5 A rated printed wiring track widths.
JUNE 2001 – REVISED JANUARY 2007
Specifications are subject to change without notice.
Customers should verify actual device performance in their specific applications.
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